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A 12-bit -channel pipeline ADC WITH 81 DB SFDR in 250 MS/s single0.13 UM CMOS

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dc.contributor.author Gu Jianhua
dc.contributor.author Yan Guojun
dc.contributor.author Ben Nengjun
dc.date.accessioned 2020-03-30T11:30:10Z
dc.date.available 2020-03-30T11:30:10Z
dc.date.issued 2018
dc.identifier.citation A 12-bit 250 MS/s single-channel pipeline ADC WITH 81 DB SFDR in 0.13 UM CMOS / Gu Jianhua, Yan Guojun, Ben Nengjun // Управління розвитком складних систем : зб. наук. праць / Київ. нац. ун-т буд-ва і архітектури ; гол. ред. Лізунов П. П. – Київ : КНУБА, 2018. – № 36. – С. 153-158. - Бібліогр. : 10 назв. uk_UA
dc.identifier.issn 2219-5300
dc.identifier.uri http://repositary.knuba.edu.ua:8080/xmlui/handle/987654321/2017
dc.description.abstract A 12bit 250-MS/s pipeline ADC is presented and fabricated in 0.13um CMOS process. A power efficient bootstrap switch with a buffer is proposed for high speed considerations. It utilizes a source follower to insulate the residue amplifier and the large capacitor in the bootstrap switch. Techniques of lightening load capacitance of each stage are proposed to speed up the corresponding residue amplifiers (RA). A clock generator and optimized timing are proposed to achieve low jitter and improve sampling linearity by saving more time for the input switch. The reference buffer and clock buffer are both fully integrated. The signal-to-distortion-and-noise-ratio (SNDR) is evaluated adopting a proper scheme and verified by the measured results. The measured SNDR is 63 dB and spurious free dynamic range (SFDR) is 81dB with 39 MHz. The core area is 2 mm2 and the ADC consumes 160 mW at 1.3V. uk_UA
dc.language.iso en uk_UA
dc.publisher КНУБА uk_UA
dc.subject pipeline ADC uk_UA
dc.subject bootstrap switches uk_UA
dc.subject reference buffer uk_UA
dc.subject clock buffer uk_UA
dc.subject timing uk_UA
dc.title A 12-bit -channel pipeline ADC WITH 81 DB SFDR in 250 MS/s single0.13 UM CMOS uk_UA
dc.type Article uk_UA
dc.subject.udc 621.372.541.061 uk_UA


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