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A 12-bit -channel pipeline ADC WITH 81 DB SFDR in 250 MS/s single0.13 UM CMOS
(КНУБА, 2018) Gu Jianhua; Yan Guojun; Ben Nengjun
A 12bit 250-MS/s pipeline ADC is presented and fabricated in 0.13um CMOS process. A power efficient bootstrap switch with a buffer is proposed for high speed considerations. It utilizes a source follower to insulate the residue amplifier and the large capacitor in the bootstrap switch. Techniques of lightening load capacitance of each stage are proposed to speed up the corresponding residue amplifiers (RA). A clock generator and optimized timing are proposed to achieve low jitter and improve sampling linearity by saving more time for the input switch. The reference buffer and clock buffer are both fully integrated. The signal-to-distortion-and-noise-ratio (SNDR) is evaluated adopting a proper scheme and verified by the measured results. The measured SNDR is 63 dB and spurious free dynamic range (SFDR) is 81dB with 39 MHz. The core area is 2 mm2 and the ADC consumes 160 mW at 1.3V.