Управління технологічними процесами 153 ДСТУ Анжу, Чен, Пенфей, Чжоу. Дослідження евтектичної нуклеації та механізму росту сплаву Al-Si [Текст] / Анжу, Чен, Пенфей, Чжоу // Управління розвитком складних систем. – 2018. – № 36. – С. 148 – 152. Gu Jianhua Master of Engineering, Associate professor in School of Mechanical and Electric Engineering, orcid.org/0000-0002-2398-874X School of Mechanical and Electric Engineering, Yancheng Polytechnic College, Jiangsu Yancheng 224005, P.R. China Yan Guojun Master of Engineering, Senior Engineer in School of Mechanical and Electric Engineering, orcid.org/0000-0002-9169-8365 School of Mechatronic Engineering, Yancheng Polytechnic College, Jiangsu Yancheng 224005, P.R. China Ben Nengjun Master of Engineering, Lecturer in School of Mechanical and Electric Engineering, orcid.org/0000-0002-3166-2985 School of Mechatronic Engineering, Yancheng Polytechnic College, Jiangsu Yancheng 224005, P.R. China A 12-BIT 250 MS/S SINGLE-CHANNEL PIPELINE ADC WITH 81 DB SFDR IN 0.13 UM CMOS Abstract. A 12bit 250-MS/s pipeline ADC is presented and fabricated in 0.13um CMOS process. A power efficient bootstrap switch with a buffer is proposed for high speed considerations. It utilizes a source follower to insulate the residue amplifier and the large capacitor in the bootstrap switch. Techniques of lightening load capacitance of each stage are proposed to speed up the corresponding residue amplifiers (RA). A clock generator and optimized timing are proposed to achieve low jitter and improve sampling linearity by saving more time for the input switch. The reference buffer and clock buffer are both fully integrated. The signal-to-distortion-and-noise-ratio (SNDR) is evaluated adopting a proper scheme and verified by the measured results. The measured SNDR is 63 dB and spurious free dynamic range (SFDR) is 81dB with 39 MHz. The core area is 2 mm2 and the ADC consumes 160 mW at 1.3V. Keywords: pipeline ADC; bootstrap switches; reference buffer; clock buffer; timing Introduction In recent years, mobile communication systems require high performance ADCs to achieve over 80dB of SFDR at 100-300MS/s. Pipeline ADCs are the proper architecture of choice in such applications due to the balance of speed, resolution and power [1]. Time interleaved architectures have been commonly used to realize 250MS/s. However, these structures suffer from offset, gain, timing and bandwidth mismatches, which introduce spurs that limit the SFDR performance. Amplifier-sharing or capacitor-sharing is an effective way to improve the power efficiency of pipeline ADCs, however, the memory effects and cross-talk between successive stages degenerate the AC performance as well [2]. Switch-RA technique is also inadequate for high speed applications because of its turn-on time [3]. The 12 bit 250MS/s ADC in this paper is designed without the above techniques. A bootstrap switch with a buffer is proposed to save power. The load capacitance of each stage is also lightened to speed up the settling of residue voltages. A clock generator with low jitter is proposed and the timing of the ADC is optimized to improve sampling linearity. Based on PSS and Pnoise tools, the noise contributions of multiplying digital-to-analog (MDAC) and clock buffer are easily simulated. The ENOB is then easily calculated and further verified by the factual chip. Circuit Design ADC architecture Fig. 1 illustrates the block diagram of the proposed ADC with a dedicated sample-and-hold amplifier (SHA), 11 pipeline stages and one 2-bit flash ADC. The flip- around S/H and 1.5bit/stage MDAC have the largest feedback factor, which is beneficial for fast settling of the residue. The ADC core works under 1.3V power supply rather than the traditional 1.2V without increasing the obvious power. The power consumption for a single- stage OTA is as the following equation [4]: (1) When the power supply of the RA raises by 100mV, the overall power consumption decreases actually. Additionally, the switch-capacitor part contributes plenty of power consumption as well. The on-resistance of a Управління розвитком складних систем (36 – 2018) ISSN 2219-5300 154 MOS switch is: (2) VGS is usually near Vdd when the switch is bootstrapped, and W/L could be decreased when Vdd increases for the same Ron. As a result, the decreased average current due to smaller size consumed by the switch could offset the 100mV power addition. Furthermore, smaller sizes mean less parasitic capacitance which is beneficial for linearity. The sampling capacitor of the S/H and the first stage are both 3pF. The capacitors and sizes of RAs are scaled down by 2 in the succeeding stages. The last six stages all use the same sizes to shorten the design schedule. The input span is 1.2Vp-p, which is enough for 12 bit design. Low jitter clock buffer and high speed reference buffer are both fully integrated. Proposed bootstrap switch Bootstrap switches are widely used to reduce signal distortion by keeping the gate-source voltage of the sampling switches constant. The generic principle of bootstrap is to apply an on-chip capacitor as a battery. In one phase, this capacitor is charged to Vdd and in the other phase redistributes its charge to the gate of input transistor. However, parasitic capacitors also participate in the process of this redistribution, which makes the gate-source voltage less than the ideal Vdd. Hence, large capacitor is usually used in the bootstrap circuit. Nevertheless, large amount of capacitor overloads the preceding stage and slows down the signal settling. Figure1 – Block diagram of proposed ADC In the previous work [5] a source follower was inserted to buffer the input and the preceding stage faced relatively small capacitor. A capacitor level shift was used to cancel the dc voltage loss by the source follower. In this paper, a simple low threshold transistor is used as a source follower while causing little dc voltage loss. Fig. 2 shows the proposed bootstrap circuit. In this way no extra capacitor is needed and hence saves area and power. With the simple buffer the preceding stage confronts relatively smaller loads. A deep N-well transistor is used as an input switch to shield itself from the substrate noise. What’s more, the bulk terminal is connected to source in the sampling phase to cancel the back-gate-effect and thus improves the sampling linearity. In the amplifying phase, the bulk is connected to the ground supply to make sure that every PN junction is reverse-biased. The proposed bootstrap switches are used in the first 5 stages and in the S/H the source follower is unnecessary due to the strong drive capability outside. Ibias Vin NN1MN2 VDD VDD MN3 MN4 CboostS2 S1 S1 S2 S1 Vout Deep Nwell Low Vth Figure – 2 Proposed bootstrap switch Way of lightening load capacitors The operation speed of pipeline ADC relies mainly on the speed of the RA in each MDAC which is determined by a function of W/L and load capacitance [6]: (3) Figure 3 – Bootstrapped reset switches In the function of maximum bandwidth of the RA is derived and shown here in equation (3). When the power budged is set, the BWmax won’t improve by increasing W/L blindly. W/L of the input transistors has an optimum value as shown [6]: (4) From Eq. 3 and Eq. 4, minimum load gives minimum Wopt and maximum bandwidth with the length S/H 3pF Stage-1 1.5-bit 3pF Stage-2 1.5-bit 1.5pF Stage-11 1.5-bit 0.4pF 2-bit Flash Vin … Digital Error Correction and Calibration 2bit 12bit Clock Reference 2bit 2bit 2bit Управління технологічними процесами 155 L limited by process and current I limited by total power budget. The load capacitor Cl consists of the input capacitors of next stage and the corresponding parasitic, in which sampling capacitors are limited by kT/C noise and mismatches. The capacitance of the input of sub- ADC and reset-switches-induced parasitic still contributes about 25% of the load. Inter-metal coupling capacitors and interleaved layout floor plan are used here to realize low value capacitors. Reset switches of the output of OPAMPs are bootstrapped and quite small W/L is used to lower the induced parasitic capacitance as shown in Fig. 3. The two same NMOS transistors are connected in parallel with the source and drain terminals in opposite direction and thus make the same parasitic for the output. With the above two techniques Cl is lowered by 15%, which is essential in high speed applications. Design optimization of the clock buffer and timing Clock jitter would degenerate the performance of the ADC especially when handling high input frequencies. Clock jitter could be periodic or random, which comes from the signal source outside the chip and the on-chip clock generator. The modern advanced signal source could give a relatively pure sine wave which is often band-pass filtered further more and finally brings less than 100 fs RMS jitter. This sine wave is amplified and buffered to form a square wave by a clock buffer. It is imperative to simulate and calculate the jitter noise precisely and then minimize it. The jitter noise is given as [7]: (5) It is essential to keep the SNDR above 62 dB(ENOB=10bit) for IF sampling, for instance, 500MHz input frequency for a 1.2Vp-p signal. As a result, we need. The jitter noise is given as: (6) The clock generator is shown as in Fig. 4. The internal jitter noise is mainly caused by thermal noise and 1/f noise of the transistors. The sine wave should cross the zero point quite fast to reduce the uncertainty induced by various noise sources. Figure 4 – Schematic of clock generator Large current is consumed by the first two stages to make fast crossing. Decoupled capacitors are used to filter the bias noise and stabilize the dc current. By using PSS and Pnoise the RMS jitter is about 120 fs. The noise from power supply also influences the purity of the clock. In this work a dedicated LDO chip is used for the clock generator on the PCB to provide a clean power. Figure 5 – Schematic of improved local clock Additionally, quantities of on-chip decoupled capacitors are applied as well. Key transistors are shielded from noise in layout. The noise model of power supply is hard to make precisely. LDO and on-chip capacitors could restrain quite low and high frequency interference. Intermediate frequency like several MHz noise may still exist and is evaluated by eye-diagram. The eye-diagram of the sampling clock with the power supply disturbed by 10MHz 1mV Vp-p interference (relatively conservative estimation) is simulated. The data of the eye-diagram is peak-to-peak and then transformed to RMS format, which is 65 fs. Although this estimation is not that precise, the order of magnitude is still correct and can be used to assess the final jitter noise. Three noise sources give us the total jitter noise: noise precisely and then minimize it. The jitter noise is given as: (7) The clock is further buffered locally as shown in Fig. 5 and its outputs are shown in Fig. 6. Clk_inp Clk_inm bias Clk_out φ1 φ1P φ1x Управління розвитком складних систем (36 – 2018) ISSN 2219-5300 156 Figure 6 – Output of local clock generator S1 is from the global non-overlapping clock. P1 is cut down ahead of time for bottom-sampling trough inverters and a NAND gate. The bootstrap switch usually experiences an extra delay due to the process of charging capacitors and hence φ1 actually rises later than P1, which is shown as the dotted line of φ1 in Fig. 6. This extra delay wastes some sampling time and thus is inferior to the sampling linearity. The proposed scheme utilizes φ1x as the clock of the bootstrapped switches, which rises ahead of φ1p. Post simulation is executed for many PVT corners to ensure that φ1p falls ahead of φ1x, resulting in correct bottom sampling. The simplified and improved timing saves about 60 ps for sampling. Measurement Results The proposed ADC has been fabricated in TSMC 0.13-μm CMOS process and its chip core area is 1 mm * 2 mm. Fig.7 shows the microphotograph of the proposed ADC. Table 1 lists the noise contribution of each key module, simulated by the PSS and Pnoise tools. Table 1 – Simulated noise of each key module Bits 12 Full scaled input 0.4243V(rms) Quantized noise 84.6uV(rms) Jitter noise 56.3uV(rms) Input cap noise of S/H (input referred) 54.1uV(rms) S/H OPAMP and stage1 cap noise (input referred) 70uV(rms) Stage1 OPAMP and stage2 cap noise (input referred) 42uV(rms) Stage2 OPAMP and stage3 cap noise (input referred) 18uV(rms) Stage3 OPAMP and stage4 cap 10uV(rms) noise (input referred) Stage4 OPAMP and stage5 cap noise (input referred) 8uV(rms) Stage6 OPAMP and stage7 cap noise (input referred) 6uV(rms) Reference noise (input referred) 25uV(rms) Settling and DC accuracy 102uV(rms) Total noise (input referred) 177.4uV(rms) ENOB 10.9 bit SNDR 67dBFS Figure 7 – Chip photograph of proposed ADC Both input signal and clock signal are generated by the pure signal sources, which are then filtered by high- quality Band-pass customized filters. Two baluns are adopted to transform the single-end signal to the differential one. To minimize the phase and amplitude imbalance, a pair of baluns are connected back-to-back. The common mode level is defined by the buffer integrated in the chip. Working at 250 MS/s, the ADC achieves 80 dB SFDR and 62.64 dB SNDR with Nyquist input and 81 dB SFDR and 63.49 dB SNDR with about 39.1 MHz input, as shown in Fig. 8. The total power consumption of one single core is about 160 mW. The measured SNDR is about 3 dB inferior to the evaluated one from table 1, mainly because the parasitic from the layout design and substrate noise of the chip as well as the noise from the PCB. The symbol * means only single-channel. Table 1 summarizes and compares the performances of the proposed ADC with other works. The Waldon figure of merit (FOM) is expressed as11: (8) This work presents an intermediate FOM value while its working speed is superior to most of other listed works, probably thanks to the proposed bootstrap switches and ways of lightening load capacitance. Delay due to charging internal capacitors φ1 φ1p φ1x Управління технологічними процесами 157 Figure 8 – Measured results with (a) 39.1MHz input @ 250 MS/s and (b) Nyquist input @ 250MS/s Table 2 – Comparison with previous works Ref 8 1 9 10 This work (Measured) Tech(nm) 180 180 130 130 130 Sampling rate (MHz) 100 250 270 100 250 Resolution (bit) 14 14 12 14 12 Supply (V) 1.8 1.8 1.2 1.2 1.3 Power (mW) 223 300 250 105 160 SFDR (dB) 91 88 77 / 81 SNDR (dB) 73 68 64 71 63 FOM (fj/conv) 540 570 740 360 555 Conclusions We presented a 12 bit 250 MS/s pipeline ADC, designed and implemented on a 0.13 um CMOS process. A bootstrap switch with a buffer is proposed to improve the preceding stage’s residue settling. Ways of lightening load capacitance are also used to speed up the RA. Clock generator with an improved timing is also introduced to increase the sampling linearity. The measurement results show that it can achieve 81 dB SFDR and 63 dB SNDR. The ADC core consumes 160 mW and obtains 555 fj/cov FOM. ____________________________________________________________________________________________ References 1. Zheng, X. et al. (2016). A 14-bit 250 MS/s Sampling Pipelined ADC in 180 nm CMOS Process, IEEE Transaction on Circuit and System, I, 1381-1392. 2. Chien, Tseng et al. (2013). A 10-bit 200 MS/s Capacitor-Sharing Pipeline ADC, IEEE Transaction on Circuit and System, I, 2902-2910. 3. Fang B., Wu, J. (2013). A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation, IEEE J. Solid-State Circuits, 48, 670-683. 4. Adeniran, O.et al. (2006). An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning, IEEE Transaction on Circuit and System, I, 2485-2497. 5. Wenhua, Yang et al. (2001). A 3-V 340 mW 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE J. Solid-State Circuits, 36, 1931-1936. 6. Mehr, Iuri et al. (2000). A 55-mW 10-bit 40 MSample/s Nyquist-Rate CMOS ADC, IEEE J. Solid-State Circuits, 35, 318-325. 7. Zanchi, Alfio et al. (2005). A 16-bit 65-MS/s 3.3 V Pipeline ADC Core in SiGe BiCMOS With 78-dB SNR and 180-fs Jitter, IEEE J. Solid-State Circuits, 40, 1225-1236. 8. Cai, H et al. (2016). A CMOS Switch-capacitor 14-bit 100MS/s Pipeline ADC with Over 100-dB SFDR International Journal of Electronics, 100(1), 62-71. 9. Wang, X et al. (2017). A 12-bit 270 MS/s Pipelined ADC with SHA-Eliminating Front End, IEEE International Symposium on Circuit and Systems, 798-801. 0 20 40 60 80 100 120 Frequency [MHz] -140 -120 -100 -80 -60 -40 -20 0 Power Spectral Density SIAND = 63.49 dB ENOB = 10.254 bits SFDR = 81.51 dBc Vin = -1.07 dBFS SIAND = 62.64 dB ENOB = 10.113 bits SFDR = 79.72 dBc Vin = -0.66 dBFS P S D [ d B ] 0 20 40 60 80 100 120 Frequency [MHz] -120 -100 P S D [ d B ] -140 -80 -60 -40 -20 0 Power Spectral Density Управління розвитком складних систем (36 – 2018) ISSN 2219-5300 158 10. Larsson, A. et al. (2006). A 360 fJ/conversion-step, 14-bit 100 MS/s, Digitally Back Calibrated Pipelined ADC in 130- nm CMOS, Analog Integrated Circuit and Signal Process, 153-164. Стаття надійшла до редколегії 03.10.2018 Рецензент: д-р техн. наук, доц. О.С.Рижков, директор ТОВ “Українсько-китайський центр шовкового шляху”, Миколаїв. ______________________________________________________________________________________________________ Гу Цзяньхуа Магістр інженерії, доцент кафедри механіки та електротехніки, orcid.org/0000-0002-2398-874X Школа механіки та електротехніки, Янченский політехнічний коледж, Цзянсу Яньчэн 224005, П.Р. Китай Ян Гоюнь Магістр інженерії, старший інженер школи механіки та електротехніки, orcid.org/0000-0002-9169-8365 Школа Мехатронічного Інжинірингу, Яньченський Політехнічний Коледж, Цзянсу Яньчэн 224005, П.Р. Китай Бен Ненджун Магістр інженерії, викладач кафедри механіки та електротехніки, orcid.org/0000-0002-3166-2985 Школа Мехатронічного Інжинірингу, Яньченський Політехнічний Коледж, Цзянсу Яньчэн 224005, П.Р. Китай 12-BIT 250 MS / S ОДНОКАНАЛЬНИЙ ТРУБОПРОВІДНИЙ АЦП З 81 DB SFDR IN 0,13 UM CMOS Анотація. АЦП трубопроводу з роздільною здатністю 12 Мбіт / с, представлений та виготовлений в процесі CMOS 0.13um. Для високошвидкісних міркувань пропонується енергозберігаючий перемикач з буфером. Він використовує вихідний пристрій для ізоляції підсилювача залишків та великого конденсатора в перемикачі завантажувача. Запропоновано методики освітлення ємності навантаження на кожній стадії, щоб прискорити відповідні підсилювачі залишків (RA). Тактовий генератор та оптимізований таймер запропоновані для досягнення низького джиттера та покращення лінійності вибірки, заощаджуючи більше часу для вхідного вимикача. Референтний буфер і годинниковий буфер повністю інтегровані. Співвідношення сигнал-спотворення та шуму (SNDR) оцінюється шляхом прийняття належної схеми та перевірки вимірюваними результатами. Виміряний сигнал SNDR становить 63 дБ, а брехні – вільний динамічний діапазон (SFDR) – 81 дБ з 39 МГц. Площа ядра становить 2 мм2, а АЦП споживає 160 мВт на 1,3 В. Ключові слова: трубопровідний АЦП; завантажувальні перемикачі; еталонний буфер; годинниковий буфер; терміни ______________________________________________________________________________________________________ Link to publication APA Gu, Jianhua, Yan, Guojun & Ben, Nengjun. (2018). A 12-bit 250 ms/s single-channel pipeline ADC WITH 81 DB SFDR in 0.13 UM CMOS. Management of Development of Complex Systems, 36, 153 – 158. ДСТУ Гу Цзяньхуа. 12-BIT 250 ms/s одноканальний трубопровідний АЦП з 81 DB SFDR in 0.13 UM CMOS [Текст] / Гу Цзяньхуа, Ян Гоюнь, Бен Ненджун // Управління розвитком складних систем. – 2018. – № 36. – С. 153 – 158.